ultimo aggiornamento 29 aprile 2011

The RSC-4128 represents Sensory’s next generation mixed signal processor for speech and analog I/O. The RSC-4128 is designed to bring advanced speech I/O features to cost sensitive embedded and consumer products. Based on an 8-bit microcontroller, the RSC-4128 integrates speech-optimized digital and analog processing blocks into a single chip solution capable of accurate speech recognition; high quality, low data-rate compressed speech; and advanced music.

Products can use one or all features in a single application.

The RSC-4128 operates in tandem with Sensory Speech™ 7 firmware,

an ultra compact suite of recognition and synthesis technologies. This reduced software footprint enables, for example, products with over 150 seconds of compressed speech, multiple speaker dependent and independent vocabularies, speaker verification, and all application code built into the RSC-4128 as a single chip solution.

Revolutionary Text-to-Speaker-Independent (T2SITM) technology allows the creation of SI recognition sets by simply entering text.

In addition to improved recognition performance, the RSC-4128 provides further on-chip integration of features.

FEATURES

FULL RANGE OF SENSORY SPEECH™ 7 CAPABILITIES

•   Enhanced Word Spotting capability (10 SI or 4 SD words) in parallel

•   Noise robust Speaker Independent, Dependent & Continuous Listening recognition

•   High quality, 3.7-7.8 kbps speech synthesis & sound effects with Sensory “SX” synthesis technology

•   Speaker Verification (SVWS) – Noise robust voice biometric security

•   8 voice MIDI-compatible music synthesis coincident with speech; drum track feature enables additional voices

•   Voice record & playback

•   Audio wake up from sleep

INTEGRATED SINGLE-CHIP SOLUTION

•   8-bit microcontroller

•   On-chip 16 bit ADC, 10 bit DAC and microphone pre-amp

•   Independent, programmable Digital Filter engine

•   Uses low cost 3.58MHz crystal (internal PLL)

•   4.8 KB total RAM (256Bytes user-RAM)

•   Five timers (3 GP, 1 Watchdog, 1 Multi Tasking)

•   Twin-DMA, Vector math accelerator, and multiplier

•   External memory bus: 20-bit Address(1Mbyte), 8-bit Data

•   On chip storage for SD, SV, templates (10 templates)

•   Code security through no ROM dump capability

•   Built-in Analog Comparator Unit (4 inputs)

•   Low EMI design for FCC and CE requirements

•   24 configurable I/O lines with 10 mA (typical) outputs

•   Fully nested interrupt structure with up to 8 sources

LONG BATTERY LIFE

• 2.4 – 3.6V operation

• 12mA (typical) operating current at 3V

• 2 low power modes; 1 µA typical sleep current